(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of end point detection for the copper Chemical Mechanical Polishing process.
(2) Description of the Prior Art
In forming semiconductor devices a large number of complex processing steps are required to form particular device features, these processing steps typically use and depend on a flat surface in order to perform their operation. The creation of semiconductor devices further results in creating these devices in a number of layers of material which further complicates the required processing steps since planarity must also be maintained from layer to layer within the device structure. Good surface planarity is critically important to lithography processes since these processes depend on maintaining depth of focus. Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On-Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity.
Because dimensions if Integrated Circuit (IC) devices within advanced IC""s continue to decrease, the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices, also continue to decrease. Dimensions of conductor and interconnection elements which directly contact IC devices have typically decreased the greatest, thus becoming the smallest in dimension of conductor and interconnecting elements within advanced IC""s. These narrow conductor and interconnection elements typically comprise the first conductor or interconnection level, which contacts an integrated circuit device. First conductor levels have traditionally been formed from aluminum metal or aluminum metal alloys. First interconnection levels (i.e. first conductive contact studs) are typically formed using tungsten. Conducting lines in the era of micron and sub-micron device features must have a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomenon such as electromigration, a requirement that grows in importance as wire widths decrease. Electromigration may, under extremely high current densities, result in an electrical open and is most common in aluminum metal and aluminum metal alloy conductor and interconnect elements and has not typically been observed in interconnects made of tungsten. Although copper metal and copper metal alloys possess the high electrical conductivity and low electromigration susceptibility desired for conductor elements and interconnection elements within advanced IC""s, methods through which copper and copper metal alloys may be formed into conductor and interconnection elements within advanced IC""s are neither entirely well developed nor entirely well understood.
Copper is seen as an attractive replacement for aluminum because of its low cost and ease of processing. Copper does however present a particular problem related to copper""s high susceptibility to oxidation. Conventional photoresist processing cannot be used when the copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The motion of the wafer relative to the polishing pad creates abrasive action. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise an insulating layer of the wafer, while the size of the silicon dioxide particles controls the physical abrasion of the surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals. An importance parameter during the polishing operation is the polishing efficiency, which is the amount of material that is removed from the surface of the substrate by the CMP process as a function of time. This efficiency is dependent on the density of the pattern or the concentration of the raised areas on the surface that is being polished.
During the CMP process, the allocated polishing time and the downforce exerted on a wafer that is being polished are typically fixed and independent of the topography of the surface that is being polished. The removal rate of material from a wafer has been shown to be directly proportional to the downward force exerted on the surface that is being polished and inversely proportional to the surface area that comes into contact with the polishing pad. The removal rate of material therefore increases as the polished surface decreases, and visa versa. Since different integrated circuits have different surface topographies, the material removed during a CMP process may vary from substrate to substrate and between various layers within a device structure.
The use of metals to interconnect the various elements of a semiconductor device as either intra-level or inter-level connectors has also required considerable attention. Electrical conductors are made of electrically conductive material, a suitable material includes Al, Al alloy, Cu, Cu alloy, Ag, Ag alloy, Si, Ti, Ta, W (tungsten), W alloy, Mo, polysilicon, or a combination thereof and oxides of these metals. Aluminum is typically used as a conductive material, however the use of tungsten and copper for conducting lines or inter-level vias has gained considerable attention in recent years.
Aluminum is typically used in upper-layer wiring. Since however copper has lower resistivity, the use of copper for conductive interfaces is being investigated. Copper is however very difficult to process by Reactive Ion Etch (RIE), the CMP method has therefore been studied for using copper as a wiring material. To polish copper at a high rate of polishing efficiency without causing surface scratching, the copper etch rate must be raised by increasing the amount of the component in the polishing slurry that is responsible for copper etching. If this component is increased to a high level, the etching will become an isotropic etch. Under these conditions, buried copper is etched away causing dishing in the wiring. It is therefore difficult to form highly reliable LSI copper wiring.
The use of copper has become increasingly more important for the creation of multilevel interconnections in semiconductor circuits, however copper lines frequently show damage after CMP and clean. This damage of copper lines causes planarization problems of subsequent layers that are deposited over the copper lines because these layers may now be deposited on a surface of poor planarity. Particularly susceptible to damage are isolated copper lines or copper lines that are adjacent to open fields. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
Current technology makes frequent use of contact plugs that use tungsten or, more recently, copper as filler for the contact openings. A sequence of layers is typically deposited inside the opening for the plug; this process will be highlighted below.
For the formation of metal contact holes, the process typically starts with the deposition of an insulating layer, openings are patterned into this layer in the areas where electrical contacts must be established with the active devices. Next a glue layer (also called seed layer) is deposited on the sidewalls and bottom of the created openings over which a barrier layer (also called nucleation layer) is deposited. The barrier layer serves the purpose of preventing gasses, that are created during the metal deposition, from penetrating into the metal that is being deposited and, in doing so, cause surface dislocations on the deposited metal. Applying a Rapid Thermal Anneal (RTA) immediately after the barrier layer has been deposited and before the metal is deposited can enhance the deposition of the barrier layer. The RTA improves the surface conformity of the deposited barrier layer. With increasingly smaller device dimensions, Chemical Vapor Deposition (CVD) techniques offer the advantage of providing good conformity independent of the thickness of the deposited barrier layer. The deposited layer of metal is etched back. Depositing a layer of a conducting material, for instance aluminum, and patterning this layer into the desired interconnecting pattern can then complete the process of metalization.
The sequence of layers in the hole for the metal plug is now as follows, starting from the bottom of the hole: a seed or glue layer, a nucleation or barrier layer and the metal plug.
FIG. 1 show a cross section of the apparatus used for Prior Art copper CMP end point detection. A laser 10 is mounted such that the laser beam 24 strikes the plane of the polishing table 12 and the polishing pad 14 under an angle that is not perpendicular with the plane of the polishing table 16. It is assumed that the plane of the polishing table 12 is parallel to the plane of the polishing pad 14. The laser beam 24 penetrates the polishing table 12 and the polishing pad 14 and strikes the surface 18 of metal that has been deposited on the surface of wafer 16. The wafer 16 is held and rotated in the conventional manner by the wafer carrier 20 that is mounted on its shaft or axis 22. The laser beam 24 is reflected (26) by the metal surface 18 of wafer 16, the reflected laser beam is captured and its intensity is measured. A high level of reflectivity indicates a that layer of metal 18 on the surface of the wafer 16, with continued application of the CMP the thickness of the metal layer 18 decrease and, with it, the intensity of the reflected laser beam. When this intensity reaches a certain minimum level, the thickness of the metal layer 18 is reduced to its desired value and the process of CMP of the copper layer is terminated. For metal polishing, all of the deposited metal is typically removed from the surface that is being polished resulting in very low reflection of the laser beam. Only the metal pattern that is desired, such as vias or a metal line pattern, remains exposed to the impending laser beam and will, as such, cause a low level of reflectivity by the surface that is being polished.
U.S. Pat. No. 5,836,805 (Obeng) teaches a CMP endpoint method by analyzing the waste slurry for conductivity, luminescence and/or particulate mass.
U.S. Pat. No. 4,147,564 (Magee et al.) shows an ionizing radiation after a polish step.
U.S. Pat. No. 5,722,875 (Iwashita et al.) shows a CU CMP with endpoint with temperature.
U.S. Pat. No. 5,637,185 (Murarka et al.) discloses a CMP endpoint process based on conductivity of waste slurry.
A principle objective of the invention is to provide a method of endpoint detection for copper CMP.
It is another objective of the invention to provide a more sensitive method of endpoint detection for copper CMP.
It is another objective of the invention to provide a method other than optical endpoint detection for copper CMP.
It is a further objective of the invention to eliminate inaccuracies in endpoint measurement of copper CMP due to underlying layer surface irregularities.
In accordance with the objectives of the invention, a method is provided whereby copper isotope is added to the deposited layer of copper.
The intensity of the radioactivity of the copper isotope is time dependent and, after initially being at a constant value, decreases rapidly as a function of time.
Under the first embodiment of the invention, a copper isotope is added to the layer of copper that is deposited to form the metal interface. While the copper layer is etched, the radioactivity emitted by the copper layer will decrease since the volume of copper of the layer decreases. Endpoint of the copper CMP is reached at the time when the copper radioactivity starts to rapidly decrease.
Under the second embodiment of the invention, a copper isotope is added to the layer of copper that is deposited to form the metal interface. While the copper layer is etched, the radioactive copper will be removed from the surface that is being planarized and will be removed as copper residue. During copper surface CMP the level of radioactivity in the copper residue will increase. Endpoint of the copper CMP is reached at the time when the radioactivity in the copper residue has increased to a predetermined level.
Under the third embodiment of the invention, a copper isotope is added to the seed layer that has been deposited prior to the deposition of a layer of copper. The deposited layer of copper shields the seed layer and therefore inhibits radioactive radiation. As the copper layer is being polished, its thickness decreases and the radioactive radiation of the seed layer increases. When this radioactive radiation starts to rapidly increase, the copper CMP is considered complete.